1. Field of the Invention
This invention relates to integrated circuits (ICs) having repetitive cells designed to be matched for proper circuit operation. More particularly, this invention relates to such integrated circuits having means to reduce the adverse effects of cell mismatch on circuit operation.
2. Description of the Prior Art
There are many integrated circuits which include a large number of repetitive cells designed to perform in matched fashion so as to assure specified circuit performance. Such cells often include impedance elements such as resistors which are for example supplied by current sources to produce corresponding output signals. Analog-to-digital (A/D) and digital-to-analog (D/A) converters are examples of devices which frequently incorporate such repetitive cells.
One problem which often arises with such integrated circuits is that in a practical device the actual match between cells turns out to be less than wanted, so that the device performance is less than satisfactory. For example, in A/D converters of the flash type, mismatch between repetitive cells typically forming part of the comparators conventionally used in such converters will adversely affect the differential and integral linearity of the digital output. Thus, in any group of processed monolithic chips having such integrated circuits, the number of parts meeting specifications for high-grade performance may be much smaller than desired due to random mismatches caused by small deviations from nominal in the parameters of some of the circuit elements.
Attempts have been made to solve this problem of mismatch between repetitive cells in an integrated circuit, but the results of such attempts have not been satisfactory. Accordingly, it is a principal object of this invention to solve this problem by the use of improved techniques for substantially reducing the effects of such mismatches.